Bitfields for AMD-640 Non-Cacheable Control Register |
| Bit | Description | ||||||
|---|---|---|---|---|---|---|---|
|
7 |
segment C000h-C7FFh cacheable and write-protected | ||||||
|
6 |
D000h-DFFFh cacheable and write-protected | ||||||
|
5 |
E000h-EFFFh cacheable and write-protected | ||||||
|
4 |
F000h-FFFFh cacheable and write-protected | ||||||
|
3 |
reserved (0) | ||||||
|
2 |
force L2 cache fill | ||||||
|
1 |
reserved (1) | ||||||
|
0 |
L2 write mode:
|
|
See Also: |