Bitfields for AMD-640 Cache Control Register 2 |
Bit | Description | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
7 - 6 |
reserved (0) | ||||||||||||
5 |
backoff processor until L2 cache filled | ||||||||||||
4 |
reserved (0) | ||||||||||||
3 |
two banks of SRAM instead of one | ||||||||||||
2 |
reserved (0) | ||||||||||||
1 - 0 |
L2 cache size
|
See Also: |