Format of PCI Configuration Data for Intel 82371AB (PIIX4), Power Management |
| Offset | Size | Description |
|---|---|---|
|
00h |
64 BYTEs |
header (see #00878) (vendor ID 8086h, device ID 7113h) |
|
40h |
DWORD |
base address of power-management I/O ports (same format as PCI base addresses; low bit hardwired to 1) |
|
44h |
DWORD |
initial counts of device 0-11 idle timers |
|
48h |
DWORD |
??? |
|
4Ch |
DWORD |
general-purpose input control |
|
50h |
3 BYTEs |
"device resource D" |
|
53h |
BYTE |
unused??? |
|
54h |
DWORD |
device activity event selection A |
|
58h |
DWORD |
device activity event selection B |
|
5Ch |
DWORD |
"device resource A" |
|
60h |
DWORD |
"device resource B" |
|
64h |
DWORD |
"device resource C" |
|
68h |
3 BYTEs |
"device resource E" |
|
6Bh |
5 BYTEs |
unused??? |
|
70h |
3 BYTEs |
"device resource G" |
|
73h |
BYTE |
unused??? |
|
74h |
DWORD |
"device resource H" |
|
78h |
DWORD |
"device resource I" |
|
7Ch |
DWORD |
"device resource J" |
|
80h |
BYTE |
miscellaneous power management |
|
81h |
15 BYTEs |
unused??? |
|
90h |
DWORD |
base address for SMBus I/O ports (same format as PCI base addresses; low bit hardwired to 1) |
|
94h |
... |
|
|
D2h |
BYTE |
SMBus host configuration |
|
D3h |
BYTE |
SMBus slave command |
|
D4h |
BYTE |
SMBus slave shadow port 1 address |
|
D5h |
BYTE |
SMBus slave shadow port 2 address |
|
D6h |
BYTE |
SMBus revision |
|
D7h |
|
|
See Also: |