Format of PCI Configuration data for Intel 82425EX PSC

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Offset	Size	Description
00h	64 BYTEs	header (see #00878) (vendor ID 8086h, device ID 0486h)
40h	BYTE	PCI control register (see #01084)
41h	3 BYTEs	???
44h	BYTE	host device control register (see #01085)
45h	3 BYTEs	???
48h	WORD	PCI local-bus IDE control register (see #01086)
4Ah	2 BYTEs	???
4Ch	BYTE	ISA I/O recovery timer register (see #01087)
4Dh	BYTE	part revision register (see #01088)
4Eh	BYTE	X-bus Chip Select A register (see #01089)
4Fh	BYTE	X-bus Chip Select B register??? (see also #01102)
50h	BYTE	host select register
51h	BYTE	deturbo frequency control register when deturbo mode is selected (see PORT 0CF9h), the chipset places a hold on the memory bus for a fraction of the time inversely proportional to the value in this register (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
52h	WORD	secondary (L2) cache control register
54h	2 BYTEs	???
56h	WORD	DRAM control register
58h	BYTE	???
59h	7 BYTEs	Programmable Attribute Map (PAM) registers 0-6 (see also #01118)
60h	5 BYTEs	DRAM row boundary registers 0-4 each register N indicates amount of memory in rows 0-N (each row is 64 bits wide); the fifth row of memory (if implemented) must contain either 8M or 16M, depending on system configuration boundary register 4 (offset 64h) contains the total system memory, which may not exceed 128M
65h	BYTE	???
66h	BYTE	PIRQ route control register 0
67h	BYTE	PIRQ route control register 1
68h	BYTE	DRAM memory hole register
69h	BYTE	top of memory
6Ah	6 BYTEs	???
70h	BYTE	SMRAM control register
71h	47 BYTEs	unused???
A0h	BYTE	SMI control register
A1h	BYTE	???
A2h	WORD	SMI enable register
A4h	DWORD	system event enable
A8h	BYTE	fast off timer register
A9h	BYTE	???
AAh	WORD	SMI request register
ACh	BYTE	clock throttle STPCLK# low timer
ADh	BYTE	unused???
AEh	BYTE	clock throttle STPCLK# high timer
AFh	BYTE	???
B0h	80 BYTEs	unused???

See Also:

#00878,#01063,#01055,#01108,#01167