Bitfields for PCI Configuration Command Register |
| Bit | Description |
|---|---|
|
0 |
I/O access enabled |
|
1 |
memory access enabled |
|
2 |
bus master enable |
|
3 |
special cycle recognition enabled |
|
4 |
memory write and invalidate enabled |
|
5 |
VGA palette snoop enabled |
|
6 |
parity error response enabled |
|
7 |
wait cycles enabled |
|
8 |
system error (SERR# line) enabled |
|
9 |
fast back-to-back transactions enabled |
|
10 - 15 |
reserved |
|
See Also: |