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Format of PCI Configuration Data

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Offset Size Description

00h

WORD

vendor ID (read-only) (see #00732 at AX=B102h)
FFFFh returned if requested device non-existent

02h

WORD

device ID (read-only)

04h

WORD

command register (see #00879)

06h

WORD

status register (see #00880)

08h

BYTE

revision ID

09h

3 BYTEs

class code:
bits 7 - 0 : programming interface
bits15 - 8 : sub-class
bits 23 - 16 : class code

0Ch

BYTE

cache line size

0Dh

BYTE

latency timer

0Eh

BYTE

header type:
bits 6 - 0 : header format
00h - other
01h - PCI-to-PCI bridge
02h - PCI-to-CardBus bridge
bit 7 : multi-function device

0Fh

BYTE

Built-In Self-Test result (see #00881)

---header type 00h---

10h

DWORD

base address 0 (see #00882) (OpenHCI) base address of host controller registers (see #00902)

14h

DWORD

base address 1

18h

DWORD

base address 2

1Ch

DWORD

base address 3

20h

DWORD

base address 4

24h

DWORD

base address 5

28h

DWORD

CardBus CIS pointer (read-only) (see #00889)

2Ch

WORD

subsystem vendor ID or 0000h

2Eh

WORD

subsystem ID or 0000h

30h

DWORD

expansion ROM base address (see #00883)

34h

BYTE

offset of capabilities list within configuration space (R/O)
(only valid if status register bit 4 set) (see #00884)

35h

3 BYTEs

reserved

38h

DWORD

reserved

3Ch

BYTE

interrupt line:
00h = none
01h = IRQ1
02h = IRQ2
03h = IRQ3
04h = IRQ4
05h = IRQ5
06h = IRQ6
07h = IRQ7
08h = IRQ8
09h = IRQ9
0Ah = IRQ10
0Bh = IRQ11
0Ch = IRQ12
0Dh = IRQ13
0Eh = IRQ14
0Fh = IRQ15

3Dh

BYTE

interrupt pin (read-only) (00h = none, else indicates INTA# to INTD#)

3Eh

BYTE

minimum time bus master needs PCI bus ownership, in 250ns units (read-only)

3Fh

BYTE

maximum latency, in 250ns units (bus masters only) (read-only)

40h

48 DWORDs

varies by device (see #00919,#00920,#01055,#01083)

---header type 01h---

10h

DWORD

base address 0 (see #00882)

14h

DWORD

base address 1

18h

BYTE

primary bus number (for bus closer to host processor)

19h

BYTE

secondary bus number (for bus further from host processor)

1Ah

BYTE

subordinate bus number

1Bh

BYTE

secondary latency timer

1Ch

BYTE

I/O base (see #00899)

1Dh

BYTE

I/O limit (see #00899)

1Eh

WORD

secondary status

20h

WORD

memory base (see #00900)

22h

WORD

memory limit

24h

WORD

prefetchable memory base

26h

WORD

prefetchable memory limit

28h

DWORD

prefetchable base, upper 32 bits

2Ch

DWORD

prefetchable limit, upper 32 bits

30h

WORD

I/O base, upper 16 bits

32h

WORD

I/O limit, upper 16 bits

34h

DWORD

reserved

38h

DWORD

expansion ROM base address

3Ch

BYTE

interrupt line

3Dh

BYTE

interrupt pin (read-only)

3Eh

WORD

bridge control (see #00901)

40h

48 DWORDs

varies by device (see #00919,#00920,#01055,#01083)

---header type 02h---

10h

DWORD

CardBus Socket/ExCa base address (see #00890)
bits 31 - 12 : start address of socket interface register block in 4K blocks
bits 11 - 0 : reserved (0)

14h

BYTE

offset of capabilities list within configuration space (R/O) (only valid if status register bit 4 set) (see #00884)

15h

BYTE

reserved

16h

WORD

secondary status

18h

BYTE

PCI bus number

19h

BYTE

CardBus bus number

1Ah

BYTE

subordinate bus number

1Bh

BYTE

CardBus latency timer

1Ch

DWORD

memory base address 0

20h

DWORD

memory limit 0

24h

DWORD

memory base address 1

28h

DWORD

memory limit 1

2Ch

WORD

I/O base address 0

2Eh

WORD

I/O base address 0 high word (optional)

30h

WORD

I/O limit 0

32h

WORD

I/O limit 0 high word (optional)

34h

WORD

I/O base address 1

36h

WORD

I/O base address 1 high word (optional)

38h

WORD

I/O limit 1

3Ah

WORD

I/O limit 1 high word (optional)

3Ch

BYTE

interrupt line

3Dh

BYTE

interrupt pin (read-only) (no interrupt used if 00h)

3Eh

WORD

bridge control

40h

WORD

subsystem vendor ID

42h

WORD

subsystem device ID

44h

DWORD

16-bit PC Card legacy mode base address (for accessing ExCa registers)

48h

14 DWORDs

reserved

80h

32 DWORDs

varies by device (see #00919,#00920,#01055,#01083)

Note:

See Also: