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Code Mnemonic Description
D0 /4 SAL r/m8, 1 Multiply r/m8 by 2, once
D2 /4 SAL r/m8, CL Multiply r/m8 by 2, CL times
C0 /4 ib SAL r/m8, imm8 Multiply r/m8 by 2, imm8 times
D1 /4 SAL r/m16, 1 Multiply r/m16 by 2, once
D3 /4 SAL r/m16, CL Multiply r/m16 by 2, CL times
C1 /4 ib SAL r/m16, imm8 Multiply r/m16 by 2, imm8 times
D1 /4 SAL r/m32, 1 Multiply r/m32 by 2, once
D3 /4 SAL r/m32, CL Multiply r/m32 by 2, CL times
C1 /4 ib SAL r/m32, imm8 Multiply r/m32 by 2, imm8 times
D0 /7 SAR r/m8, 1 Signed divide* r/m8 by 2, once
D2 /7 SAR r/m8, CL Signed divide* r/m8 by 2, CL times
C0 /7 ib SAR r/m8, imm8 Signed divide* r/m8 by 2, imm8 times
D1 /7 SAR r/m16, 1 Signed divide* r/m16 by 2, once
D3 /7 SAR r/m16, CL Signed divide* r/m16 by 2, CL times
C1 /7 ib SAR r/m16, imm8 Signed divide* r/m16 by 2, imm8 times
D1 /7 SAR r/m32, 1 Signed divide* r/m32 by 2, once
D3 /7 SAR r/m32, CL Signed divide* r/m32 by 2, CL times
C1 /7 ib SAR r/m32, imm8 Signed divide* r/m32 by 2, imm8 times
D0 /4 SHL r/m8, 1 Multiply r/m8 by 2, once
D2 /4 SHL r/m8, CL Multiply r/m8 by 2, CL times
C0 /4 ib SHL r/m8, imm8 Multiply r/m8 by 2, imm8 times
D1 /4 SHL r/m16, 1 Multiply r/m16 by 2, once
D3 /4 SHL r/m16, CL Multiply r/m16 by 2, CL times
C1 /4 ib SHL r/m16, imm8 Multiply r/m16 by 2, imm8 times
D1 /4 SHL r/m32, 1 Multiply r/m32 by 2, once
D3 /4 SHL r/m32, CL Multiply r/m32 by 2, CL times
C1 /4 ib SHL r/m32, imm8 Multiply r/m32 by 2, imm8 times
D0 /5 SHR r/m8, 1 Unsigned divide r/m8 by 2, once
D2 /5 SHR r/m8, CL Unsigned divide r/m8 by 2, CL times
C0 /5 ib SHR r/m8, imm8 Unsigned divide r/m8 by 2, imm8 times
D1 /5 SHR r/m16, 1 Unsigned divide r/m16 by 2, once
D3 /5 SHR r/m16, CL Unsigned divide r/m16 by 2, CL times
C1 /5 ib SHR r/m16, imm8 Unsigned divide r/m16 by 2, imm8 times
D1 /5 SHR r/m32, 1 Unsigned divide r/m32 by 2, once
D3 /5 SHR r/m32, CL Unsigned divide r/m32 by 2, CL times
C1 /5 ib SHR r/m32, imm8 Unsigned divide r/m32 by 2, imm8 times

Description
Shifts the bits in the first operand (destination operand) to the left or right by the number of bits specified in the second operand (count operand). Bits shifted beyond the destination operand boundary are first shifted into the CF flag, then discarded. At the end of the shift operation, the CF flag contains the last bit shifted out of the destination operand.

The destination operand can be a register or a memory location. The count operand can be an immediate value or register CL. The count is masked to 5 bits, which limits the count range to 0 to 31. A special opcode encoding is provided for a count of 1.

The shift arithmetic left (SAL) and shift logical left (SHL) instructions perform the same operation; they shift the bits in the destination operand to the left (toward more significant bit loca-tions). For each shift count, the most significant bit of the destination operand is shifted into the CF flag, and the least significant bit is cleared (see Figure 6-6 in the Intel Architecture Software Developer's Manual, Volume 1).

The shift arithmetic right (SAR) and shift logical right (SHR) instructions shift the bits of the destination operand to the right (toward less significant bit locations). For each shift count, the least significant bit of the destination operand is shifted into the CF flag, and the most significant bit is either set or cleared depending on the instruction type. The SHR instruction clears the most significant bit (see Figure 6-7 in the Intel Architecture Software Developer's Manual, Volume 1); the SAR instruction sets or clears the most significant bit to correspond to the sign (most signif-icant bit) of the original value in the destination operand. In effect, the SAR instruction fills the empty bit position's shifted value with the sign of the unshifted value (see Figure 6-8 in the Intel Architecture Software Developer's Manual, Volume 1).

The SAR and SHR instructions can be used to perform signed or unsigned division, respectively, of the destination operand by powers of 2. For example, using the SAR instruction to shift a signed integer 1 bit to the right divides the value by 2.

Using the SAR instruction to perform a division operation does not produce the same result as the IDIV instruction. The quotient from the IDIV instruction is rounded toward zero, whereas the "quotient" of the SAR instruction is rounded toward negative infinity. This difference is apparent only for negative numbers. For example, when the IDIV instruction is used to divide -9 by 4, the result is -2 with a remainder of -1. If the SAR instruction is used to shift -9 right by two bits, the result is -3 and the "remainder" is +3; however, the SAR instruction stores only the most significant bit of the remainder (in the CF flag).

The OF flag is affected only on 1-bit shifts. For left shifts, the OF flag is cleared to 0 if the most-significant bit of the result is the same as the CF flag (that is, the top two bits of the original operand were the same); otherwise, it is set to 1. For the SAR instruction, the OF flag is cleared for all 1-bit shifts. For the SHR instruction, the OF flag is set to the most-significant bit of the original operand.
Operands Bytes Clocks
reg, 1 2 1 PU
mem, 1 2 + d(0, 2) 3 PU
reg, cl 2 4 NP
mem, cl 2 + d(0, 2) 4 NP
reg, imm 3 1 PU
mem, imm 3 + d(0, 2) 3 PU ( not pairable if there is a displacement and immediate)

Flags
ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF sets according to the result. If the count is 0, the flag is not affected
VM unaffected ZF sets according to the result. If the count is 0, the flag is not affected
RF unaffected AF undefined for a non-zero count
NT unaffected PF sets according to the result. If the count is 0, the flag is not affected
IOPL unaffected CF ontains the value of the last bit shifted out of the destination operand; it is undefined for SHL and SHR instructions where the count is greater than or equal to the size (in bits) of the destination operand
OF affected only for 1-bit shifts (see "Description" above); otherwise, it is undefined