Bitfields for Intel 82371FB/82371SB SMI Control Register |
| Bit | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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7 - 5 |
reserved | ||||||||||||
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4 - 3 |
Fast-Off Timer freeze/granularity selection
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2 |
STPCLK# scaling enable
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1 |
STPCLK# signal enable
|
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0 |
SMI# Gate
|
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Note: |
Bit 1 is cleared either with an explicit write of 0 here, or by any write to
PORT 00B2h. Bit 0 does not affect the recording of SMI events, so a pending SMI will cause an immediate SMI# when the bit is set. |
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See Also: |