Bitfields for Intel 82371MX System SMI Enable/Status registers |
| Bit | Description |
|---|---|
|
7 |
reserved |
|
6 |
Write to APMC Port (software SMI) |
|
5 |
EXTSMI# |
|
4 |
IRQ12 |
|
3 |
IRQ8 |
|
2 |
IRQ4 |
|
1 |
IRQ3 |
|
0 |
IRQ1 |
|
Note: |
Each set bit in the Enable register turns on SMI# generation for the associated hardware event; a set bit in the Status register indicates which event caused the SMI interrupt. |
|
See Also: |