Format of PCI configuration for Intel 82371MX MPIIX |
| Offset | Size | Description |
|---|---|---|
|
00h |
64 BYTEs |
header (see #00878) (vendor ID 8086h, device ID 1234h) |
|
40h |
9 BYTEs |
reserved |
|
49h |
BYTE |
serial and parallel port enable (see #01169) |
|
4Ah |
2 BYTEs |
reserved |
|
4Ch |
BYTE |
Extended I/O Controller Recovery Timer (see #01170) |
|
4Dh |
BYTE |
reserved |
|
4Eh |
BYTE |
BIOS enable (see #01171) |
|
4Fh |
BYTE |
FDC enable (see #01172) |
|
50h |
16 BYTEs |
reserved |
|
60h |
BYTE |
PIRQA# Route Control (see #01076) |
|
61h |
BYTE |
PIRQB# Route Control (see #01076) |
|
62h |
8 BYTEs |
reserved |
|
6Ah |
WORD |
Miscellaneous Status (see #01173) |
|
6Ch |
WORD |
IDE timing modes (see #01223) |
|
6Eh |
2 BYTEs |
reserved |
|
70h |
BYTE |
Motherboard IRQ Route Control (see #01223) |
|
71h |
5 BYTEs |
reserved |
|
76h |
3 BYTEs |
Motherboard DMA Route Control (see #01219) |
|
79h |
5 BYTEs |
reserved |
|
7Eh |
BYTE |
Audio enable (see #01174) |
|
7Fh |
BYTE |
DMA channel 5-7 address size (see #01175) |
|
80h |
BYTE |
PCI DMA enable (see #01176) |
|
81h |
7 BYTEs |
reserved |
|
88h |
BYTE |
PCI DMA/PCI DMA expansion A (see #01177) |
|
89h |
BYTE |
PCI DMA/PCI DMA expansion B (see #01177) |
|
8Ah |
WORD |
Programmable Memory Address Control 0 (see #01178) |
|
8Ch |
WORD |
Programmable Memory Address Control 1 (see #01178) |
|
8Eh |
WORD |
Programmable Memory Address Mask (see #01179) |
|
90h |
BYTE |
Programmable Address Range Enable (see #01180) |
|
91h |
BYTE |
reserved |
|
92h |
WORD |
Programmable Chip Select Control (see #01181) |
|
94h |
WORD |
Programmable Address Control 1 (see #01182) |
|
96h |
WORD |
Programmable Address Control 2 (see #01182) |
|
98h |
WORD |
Programmable Address Control 3 (see #01182) |
|
9Ah |
BYTE |
Programmable Address Mask A (see #01183) |
|
9Bh |
BYTE |
Programmable Address Mask B (see #01184) |
|
9Ch |
WORD |
I/O configuration address (see #01185) |
|
9Eh |
2 BYTEs |
reserved |
|
A0h |
WORD |
Programmable Address Control 4 (see #01182) |
|
A2h |
WORD |
Programmable Address Control 5 (see #01182) |
|
A4h |
BYTE |
Programmable Address Mask C (see #01186) |
|
A5h |
BYTE |
Peripheral Access Detect Enable 0 (see #01187) |
|
A6h |
BYTE |
Peripheral Access Detect Enable 1 (see #01188) |
|
A7h |
BYTE |
Peripheral Access Detect Enable 2 (see #01189) |
|
A8h |
WORD |
Local Trap Address for Device 3 (see #01190) |
|
AAh |
BYTE |
Local Trap Mask for Device 3 (see #01191) |
|
ABh |
BYTE |
Local Trap SMI Enable (see #01192) |
|
ACh |
2 BYTEs |
reserved |
|
AEh |
BYTE |
Local Trap SMI Status (see #01192) |
|
AFh |
BYTE |
reserved |
|
B0h |
BYTE |
Local Standby SMI Enable (see #01193) |
|
B1h |
BYTE |
Local Standby Timer Reload Enable (see #01194) |
|
B2h |
BYTE |
Local Standby SMI Status (see #01193) |
|
B3h |
BYTE |
reserved |
|
B4h |
BYTE |
Local Standby Timer IDE Idle (see #01195) |
|
B5h |
BYTE |
Local Standby Timer Audio Idle (see #01195) |
|
B6h |
BYTE |
Local Standby Timer COM Idle (see #01195) |
|
B7h |
BYTE |
reserved |
|
B8h |
BYTE |
Local Standby Timer Device 1 Idle (see #01195) |
|
B9h |
BYTE |
Local Standby Timer Device 2 Idle (see #01195) |
|
BAh |
BYTE |
Local Standby Timer Device 3 Idle (see #01195) |
|
BBh |
BYTE |
reserved |
|
BCh |
BYTE |
Software/EXTSMI# SMI Delay Timer (see #01195) |
|
BDh |
BYTE |
Suspend SMI Delay Timer (see #01195) |
|
BEh |
BYTE |
Global Standby Timer (see #01195) |
|
BFh |
BYTE |
Clock Throttle Standby Timer (see #01195) |
|
C0h |
BYTE |
System Management Control (see #01196) |
|
C1h |
BYTE |
System SMI Enable (see #01197) |
|
C2h |
BYTE |
Miscellaneous SMI Enable (see #01198) |
|
C3h |
BYTE |
Global SMI Enable (see #01200) |
|
C4h |
2 BYTEs |
reserved |
|
C6h |
BYTE |
System SMI Status (see #01197) |
|
C7h |
BYTE |
Miscellaneous SMI Status (see #01199) |
|
C8h |
BYTE |
Global SMI Status (see #01201) |
|
C9h |
3 BYTEs |
reserved |
|
CCh |
BYTE |
Suspend/Resume Control 1 (see #01202) |
|
CDh |
BYTE |
Suspend/Resume Control 2 (see #01203) |
|
CEh |
BYTE |
SMOUT Control (see #01204) |
|
CFh |
BYTE |
reserved |
|
D0h |
BYTE |
System Event Enable 0 (see #01207) |
|
D1h |
BYTE |
System Event Enable 1 (see #01208) |
|
D2h |
BYTE |
System Event Enable 2 (see #01209) |
|
D3h |
BYTE |
Burst Count Timer (see #01195) |
|
D4h |
BYTE |
Clock Control (see #01205) |
|
D5h |
BYTE |
reserved |
|
D6h |
BYTE |
STPCLK# Low Timer (see #01195) |
|
D7h |
BYTE |
STPCLK# High Timer (see #01195) |
|
D8h |
BYTE |
Stop Break Event Enable 0 (see #01207) |
|
D9h |
BYTE |
Stop Break Event Enable 1 (see #01208) |
|
DAh |
BYTE |
Stop Break Event Enable 2 (see #01209) |
|
DBh |
5 BYTEs |
reserved |
|
E0h |
BYTE |
Shadow Register (see #01206) |
|
E1h |
3 BYTEs |
reserved |
|
Eh |
BYTE |
Burst Clock Event Enable 0 (see #01207) |
|
E5h |
BYTE |
Burst Clock Event Enable 1 (see #01208) |
|
E6h |
BYTE |
Burst Clock Event Enable 2 (see #01209) |
|
E7h |
BYTE |
Burst Clock Event Enable 3 (see #01210) |
|
E8h |
BYTE |
Burst Clock Event Enable 4 (see #01211) |
|
E9h |
BYTE |
Burst Clock Event Enable 5 (see #01212) |
|
EAh |
BYTE |
Burst Clock Event Enable 6 (see #01213) |
|
EBh |
BYTE |
reserved |
|
ECh |
BYTE |
Clock Throttle Break Event Enable 0 (see #01207) |
|
EDh |
BYTE |
Clock Throttle Break Event Enable 1 (see #01208) |
|
EEh |
BYTE |
Clock Throttle Break Event Enable 2 (see #01209) |
|
EFh |
BYTE |
Clock Throttle Break Event Enable 3 (see #01210) |
|
F0h |
BYTE |
Clock Throttle Break Event Enable 4 (see #01211) |
|
F1h |
BYTE |
Clock Throttle Break Event Enable 5 (see #01212) |
|
F2h |
BYTE |
Clock Throttle Break Event Enable 6 (see #01213) |
|
F3h |
13 BYTES |
reserved |
|
See Also: |