Format of PCI configuration for Intel 82443EX/LX Device 0 (Host-PCI)

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Offset	Size	Description
00h	64 BYTEs	header (see #00878) (vendor ID 8086h, device ID 7180h) chipset is 82443EX if revision >= 03h
40h	16 BYTEs	reserved
50h	WORD	PAC Configuration register (See #01131)
52h	BYTE	reserved
53h	BYTE	Data Buffer Control register (see #01132)
54h	BYTE	reserved
55h	WORD	DRAM Row Type register (see #01133)
57h	BYTE	DRAM Control register (see #01134)
58h	BYTE	DRAM Timing register (see #01135)
59h	7 BYTEs	PAM Configuration registers 0-6 (See #01118)
60h	8 BYTEs	DRAM Row Boundary registers 0-7 each register indicates top of memory for a particular row, in 8MB units; DIMMs use two rows each, with single-sided DIMMs leaving the odd-numbered rows unpopulated
68h	BYTE	Fixed DRAM Hole Control register (see #01147)
69h	BYTE	reserved
6Ah	WORD	DRAM Extended Mode Select register (see #01136)
6Ch	DWORD	Memory Buffer Strength Control register (see #01137)
70h	BYTE	Multi-Transaction Timer register (see #01140)
71h	BYTE	reserved
72h	BYTE	System Management RAM Control register (see #01123)
73h	29 BYTEs	reserved
90h	BYTE	Error Command register (see #01156)
91h	BYTE	Error Status 0 register (see #01138)
92h	BYTE	Error Status 1 register (see #01139)
93h	BYTE	Reset Control Register (see #01239)
94h	12 BYTEs	reserved
A0h	DWORD	AGP Capability register (see #01158)
A4h	DWORD	AGP Status register (see #01159)
A8h	DWORD	AGP Command register (see #01160)
ACh	4 BYTEs	reserved
B0h	DWORD	AGP Control register (see #01161)
B4h	BYTE	Arpeture Size Control register (see #01162)
B5h	3 BYTEs	reserved
B8h	DWORD	Arpeture Translation Table Base register (see #01163)
BCh	BYTE	AGP MTT Control register (see #01140)
BDh	BYTE	AGP Low Priority Transaction timer register (see #01141)
BEh	67 BYTEs	reserved

Note:	The 82443EX is virtually identical to the 82443LX, except that it does not support ECC type DRAM. The Intel 82443EX/LX chipsets use PCI configuration mechanism.
See Also:	#01130,#01142