[ Up ] [ Docs Home ]

Bitfields for Intel 82378/82379 SMI Control Register

[ Back ] [ Next ]
Bit Description

7

reserved

6

(82378) reserved
(82379) require Stop Grant bus cycle before asserting STPCLK#

5 - 4

reserved

3

Fast-Off Timer freeze

2

STPCLK# scaling enable
1 = enable Clock Throttle bytes in PCI configuration space

1

STPCLK# signal enable
1 = assert STPCLK# on read from PORT 00B2h

0

SMI# Gate
1 = enable SMI# on system management interrupt

Note:

Bit 1 is cleared either with an explicit write of 0 here, or by any write to PORT 00B2h.
Bit 0 does not affect the recording of SMI events, so a pending SMI will cause an immediate SMI# when the bit is set.

See Also:

#01064,#01080,#01081,#01222