Format of PCI Configuration data for Intel 82424 Cache Controller

[ Back ] [ Next ]

Offset	Size	Description
00h	64 BYTEs	header (see #00878) (vendor ID 8086h, device ID 0483h)
40h	BYTE	bus number
41h	BYTE	subordinate bus number
42h	BYTE	disconnect timer
50h	BYTE	host CPU selection
51h	BYTE	deturbo frequency control when deturbo mode is selected (see PORT 0CF9h), the chipset places a hold on the memory bus for a fraction of the time inversely proportional to the value in this register (i.e. C0h = 1/4, 80h = 1/2, 40h = 3/4, 20h = 7/8, etc.)
52h	BYTE	secondary cache control
53h	BYTE	write buffer control
54h	BYTE	PCI features control
55h	BYTE	DRAM Operation Mode Select
56h	BYTE	System Exception Handling
57h	BYTE	SMM Control Register
58h	BYTE	reserved
59h	7 BYTEs	Programmable Attribute Map registers 0-6 (see also #01118)
60h	4 BYTEs	DRAM Row Boundary registers 0-3 each register N indicates amount of memory in rows 0-N (each row is 64 bits wide) boundary register 3 (offset 63h) contains the total system memory, which may not exceed 128M
64h	4 BYTEs	unused???
68h	WORD	Memory Hole-0
6Ah	WORD	Memory Hole-1

Note:	The above field names are those given by EduWARE's PCI Configuration Manager v1.2.
See Also:	#01055,#01083,#01108