Format of AMD-645 Peripheral Bus Controller, function 0 (PCI-ISA bridge) data |
| Offset | Size | Description |
|---|---|---|
|
00h |
64 BYTEs |
header (see #00878) (vendor ID 1106h, device ID 0586h) |
|
40h |
BYTE |
ISA bus control (see #01012) |
|
41h |
BYTE |
ISA Test Mode (see #01013) |
|
42h |
BYTE |
ISA clock control (see #01014) |
|
43h |
BYTE |
ROM Decode Control (see #01015) |
|
44h |
BYTE |
keyboard controller control (see #01016) |
|
45h |
BYTE |
Type F DMA control (see #01017) |
|
46h |
BYTE |
Miscellaneous control 1 (see #01018) |
|
47h |
BYTE |
Miscellaneous control 2 (see #01019) |
|
48h |
BYTE |
Miscellaneous control 3 (see #01020) |
|
49h |
BYTE |
reserved |
|
4Ah |
BYTE |
IDE interrupt routing (see #01021) |
|
4Bh |
BYTE |
reserved |
|
4Ch |
BYTE |
PCI memory hole bottom, bits 23-16 |
|
4Dh |
BYTE |
PCI memory hole top, bits 23-16 (if top is <= bottom, hole is disabled) |
|
4Eh |
WORD |
DMA/Master memory access control 3 (see #01022) |
|
50h |
BYTE |
PnP DRQ Routing (see #01023) |
|
51h |
3 BYTEs |
reserved |
|
54h |
BYTE |
PCI IRQ Edge/Level selection (see #01024) |
|
55h |
BYTE |
PnP Routing for external MIRQ0/1 (see #01025) |
|
56h |
BYTE |
PnP Routing for PCI INTB/INTA (see #01027) |
|
57h |
BYTE |
PnP Routing for PCI INTD/INTC (see #01028) |
|
58h |
BYTE |
PnP Routing for external MIRQ2 (see #01029) |
|
59h |
BYTE |
MIRQ pin configuration (see #01030) |
|
5Ah |
BYTE |
XD Power-On Strap Options (see #01031) |
|
5Bh |
BYTE |
internal RTC test mode (see #01032) |
|
5Ch |
4 BYTEs |
reserved |
|
60h |
WORD |
distributed DMA, channel 0 base address/enable (see #01033) |
|
62h |
WORD |
distributed DMA, channel 1 base address/enable (see #01033) |
|
64h |
WORD |
distributed DMA, channel 2 base address/enable (see #01033) |
|
66h |
WORD |
distributed DMA, channel 3 base address/enable (see #01033) |
|
68h |
WORD |
reserved |
|
6Ah |
WORD |
distributed DMA, channel 4 base address/enable (see #01033) |
|
6Ch |
WORD |
distributed DMA, channel 5 base address/enable (see #01033) |
|
6Eh |
WORD |
distributed DMA, channel 6 base address/enable (see #01033) |
|
70h |
144 BYTEs |
distributed DMA, channel 7 base address/enable (see #01033) |
|
See Also: |