| Bit |
Description |
|
7 - 6
|
segment DC00h-DFFFh shadow RAM control
| 00 |
- |
shadowing disabled |
| 01 |
- |
write enabled |
| 10 |
- |
read enabled |
| 11 |
- |
both read and write enabled |
|
|
5 - 4
|
segment D800h-DBFFh shadow RAM control
| 00 |
- |
shadowing disabled |
| 01 |
- |
write enabled |
| 10 |
- |
read enabled |
| 11 |
- |
both read and write enabled |
|
|
3 - 2
|
segment D400h-D7FFh shadow RAM control
| 00 |
- |
shadowing disabled |
| 01 |
- |
write enabled |
| 10 |
- |
read enabled |
| 11 |
- |
both read and write enabled |
|
|
1 - 0
|
segment D000h-D3FFh shadow RAM control
| 00 |
- |
shadowing disabled |
| 01 |
- |
write enabled |
| 10 |
- |
read enabled |
| 11 |
- |
both read and write enabled |
|