Bitfields for AMD-640 DRAM Configuration Register 2 |
| Bit | Description | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
7 - 5 |
type of address mapping for memory banks 4 and 5 (see #00989) | ||||||||||||||||||||||||
|
4 - 3 |
reserved (0) | ||||||||||||||||||||||||
|
2 - 0 |
last populated memory bank:
|
|
Note: |
Banks 2-4 are non-cacheable if tag RAM is ten bits + modified bit. |
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See Also: |