Format of AMD-640 System Controller |
| Offset | Size | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
|
00h |
64 BYTEs | header (see #00878) (vendor ID 1106h, device ID 0595h) | |||||||||
|
0Dh |
BYTE |
latency timer (bits 7-3):
|
|||||||||
|
40h |
16 BYTEs |
unused??? | |||||||||
|
50h |
BYTE |
cache control 1 (see #00984) | |||||||||
|
51h |
BYTE |
cache control 2 (see #00985) | |||||||||
|
52h |
BYTE |
non-cacheable control (see #00986) | |||||||||
|
53h |
BYTE |
system performance control (see #00987) | |||||||||
|
54h |
WORD |
non-cacheable region 1 (see #00988) | |||||||||
|
56h |
WORD |
non-cacheable region 2 (see #00988) | |||||||||
|
58h |
BYTE |
DRAM configuration register 1 (see #00989) | |||||||||
|
59h |
BYTE |
DRAM configuration register 2 (see #00990) | |||||||||
|
5Ah |
6 BYTEs |
end of DRAM banks 0-5 each register specifies bits 29-22 of the bank's ending address |
|||||||||
|
60h |
BYTE |
DRAM type (see #00991) | |||||||||
|
61h |
BYTE |
shadow RAM control register 1 (see #00992) | |||||||||
|
62h |
BYTE |
shadow RAM control register 2 (see #00993) | |||||||||
|
63h |
BYTE |
shadow RAM control register 3 (see #00994) | |||||||||
|
64h |
BYTE |
DRAM timing (see #00995) | |||||||||
|
65h |
BYTE |
DRAM control register 1 (see #00996) | |||||||||
|
66h |
BYTE |
DRAM control register 2 (see #00997) | |||||||||
|
67h |
BYTE |
32-bit DRAM width control register (see #00998) | |||||||||
|
68h |
2 BYTEs |
reserved | |||||||||
|
6Ah |
BYTE |
DRAM refresh counter (in units of 16 CPU clocks) | |||||||||
|
6Bh |
BYTE |
DRAM refresh control register (see #00999) | |||||||||
|
6Ch |
BYTE |
SDRAM control register (see #01000) | |||||||||
|
6Dh |
BYTE |
DRAM drive strength control register (see #01001) | |||||||||
|
6Eh |
BYTE |
ECC control register (see #01002) | |||||||||
|
6Fh |
BYTE |
ECC status register (see #01003) | |||||||||
|
70h |
BYTE |
PCI buffer control (see #01004) | |||||||||
|
71h |
BYTE |
CPU-to-PCI flow control 1 (see #01005) | |||||||||
|
72h |
BYTE |
CPU-to-PCI flow control 2 (see #01006) | |||||||||
|
73h |
BYTE |
PCI target control (see #01007) | |||||||||
|
74h |
BYTE |
PCI initiator control (see #01008) | |||||||||
|
75h |
BYTE |
PCI arbitration control 1 (see #01009) | |||||||||
|
76h |
BYTE |
PCI arbitration control 2 (see #01010) | |||||||||
|
77h |
137 BYTEs |
reserved |
|
Note: |
The AMD-640 uses PCI configuration mechanism #1; bus/device/function are always 00h/00h/00h. |
|
See Also: |