Format of PicoPower Vesuvius V3-LS ISA Bridge configuration |
| Offset | Size | Description |
|---|---|---|
|
00h |
64 BYTEs |
header (see #00878) (vendor ID 1066h, device ID 0002h or 8002h) |
|
40h |
WORD |
distributed DMA control register (see #00972) |
|
42h |
BYTE |
distributed DMA status register (see #00973) |
|
44h |
DWORD |
slave DMAC CH0 base register (see #00974) |
|
48h |
DWORD |
slave DMAC CH1 base register (see #00974) |
|
4Ch |
DWORD |
slave DMAC CH2 base register (see #00974) |
|
50h |
DWORD |
slave DMAC CH3 base register (see #00974) |
|
54h |
DWORD |
slave DMAC CH5 base register (see #00974) |
|
58h |
DWORD |
slave DMAC CH6 base register (see #00974) |
|
5Ch |
DWORD |
slave DMAC CH7 base register (see #00974) |
|
90h |
DWORD |
PCI-to-ISA bridge configuration register (see #00975) |
|
94h |
DWORD |
ISA memory address positive decode (see #00976) |
|
98h |
DWORD |
I/O address positive decode (see #00977) |
|
9Ch |
WORD |
I/O configuration address register (see #00978) |
|
A0h |
DWORD |
programmable ISA I/O address decoder (see #00979) |
|
A4h |
6 DWORD |
programmable ISA range decoder registers 1-6 (see #00980) |
|
C0h |
64 BYTEs |
reserved |
|
See Also: |