Format of National Semiconductor PC87415 IDE DMA-Master configuration |
| Offset | Size | Description |
|---|---|---|
|
00h |
64 BYTEs |
header (see #00878) (vendor ID 100Bh, device ID 0002h) |
|
40h |
3 BYTEs |
control register |
|
43h |
BYTE |
write buffer status (read-only) |
|
44h |
BYTE |
Channel 1 master read timing |
|
45h |
BYTE |
Channel 1 master write timing |
|
48h |
BYTE |
Channel 1 slave read timing |
|
49h |
BYTE |
Channel 1 slave write timing |
|
4Ch |
BYTE |
Channel 2 master read timing |
|
4Dh |
BYTE |
Channel 2 master write timing |
|
50h |
BYTE |
Channel 2 slave read timing |
|
51h |
BYTE |
Channel 2 slave write timing |
|
54h |
BYTE |
command and control block timing |
|
55h |
BYTE |
sector size |
|
See Also: |