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Code Mnemonic Description
0C ib OR AL, imm8 AL OR imm8
0D iw OR AX, imm16 AX OR imm16
0D id OR EAX, imm32 EAX OR imm32
80 /1 ib OR r/m8, imm8 r/m8 OR imm8
81 /1 iw OR r/m16, imm16 r/m16 OR imm16
81 /1 id OR r/m32, imm32 r/m32 OR imm32
83 /1 ib OR r/m16, imm8 r/m16 OR imm8 (sign-extended)
83 /1 ib OR r/m32, imm8 r/m32 OR imm8 (sign-extended)
08 / r OR r/m8, r8 r/m8 OR r8
09 / r OR r/m16, r16 r/m16 OR r16
09 / r OR r/m32, r32 r/m32 OR r32
0A / r OR r8, r/m8 r8 OR r/m8
0B / r OR r16, r/m16 r16 OR r/m16
0B / r OR r32, r/m32 r32 OR r/m32

Description
Performs a bitwise inclusive OR operation between the destination (first) and source (second) operands and stores the result in the destination operand location. The source operand can be an immediate, a register, or a memory location; the destination operand can be a register or a memory location. (However, two memory operands cannot be used in one instruction.) Each bit of the result of the OR instruction is 0 if both corresponding bits of the operands are 0; otherwise, each bit is 1.
Operands Bytes Clocks
reg, reg 2 1 UV
mem, reg 2 + d(0, 2) 3 UV
reg, mem 2 + d(0, 2) 2 UV
reg, imm 2 + i(1, 2) 1 UV
mem, imm 2 + d(0, 2) + i(1, 2) 3 UV ( not pairable if there is a displacement and immediate)
acc, imm 1 + i(1, 2) 1 UV

Flags
ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF sets according to the result
VM unaffected ZF sets according to the result
RF unaffected AF undefined
NT unaffected PF sets according to the result
IOPL unaffected CF cleared
OF cleared