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MOV - Move to/from Control Registers

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Code Mnemonic Description
0F 22 / r MOV CR0, r32 Move r32 to CR0
0F 22 / r MOV CR2, r32 Move r32 to CR2
0F 22 / r MOV CR3, r32 Move r32 to CR3
0F 22 / r MOV CR4, r32 Move r32 to CR4
0F 20 / r MOV r32, CR0 Move CR0 to r32
0F 20 / r MOV r32, CR2 Move CR2 to r32
0F 20 / r MOV r32, CR3 Move CR3 to r32
0F 20 / r MOV r32, CR4 Move CR4 to r32

Description
Moves the contents of a control register (CR0, CR2, CR3, or CR4) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See "Control Registers" in Chapter 2 of the Intel Architecture Software Devel-oper's Manual, Volume 3, for a detailed description of the flags and fields in the control regis-ters.)

When loading a control register, a program should not attempt to change any of the reserved bits; that is, always set reserved bits to the value previously read.

At the opcode level, the reg field within the ModR/M byte specifies which of the control registers is loaded or read. The 2 bits in the mod field are always 11B. The r/m field specifies the general-purpose register loaded or read.

These instructions have the following side effects:
· When writing to control register CR3, all non-global TLB entries are flushed
Operands Bytes Clocks
r32, cr32 3 4 NP
cr32, r32 3 12/22 (cycles depend on which special register) NP
r32, dr32 3 2/12 (cycles depend on which special register) NP
dr32, r32 3 11/12 (cycles depend on which special register) NP
r32, tr32 3 - NP
tr32, r32 3 - NP

Flags
ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF undefined
VM unaffected ZF undefined
RF unaffected AF undefined
NT unaffected PF undefined
IOPL unaffected CF undefined
OF undefined