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Bitfields for Intel 82437FX/82437MX PCI Control register

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Bit Description

7 - 5

 CPU inactivity timer (in PCI Clocks less 1)

4

 reserved

3

 enable PCI Peer Concurrency
0 = CPU kept off PCI bus during all PCI bus-master cycles
1 = CPU can access DRAM/L2 during non-PIIX PCI master cycles

2

 disable PCI Bursting

1

 disable PCI Streaming

0

 disable Bus Concurrency

See Also:

#01106,#01107,#01110