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Format of PCI Configuration Data for Intel 82439TX "MTXC"

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Offset Size Description

00h

64 BYTEs

header (see #00878) (vendor ID 8086h, device ID 7100h) (revision ID 00h = A0 stepping)

40h

15 BYTEs

reserved

4Fh

BYTE

Arbitration Control register (see #01109)

50h

BYTE

PCI Control register (see #01110)

51h

BYTE

reserved

52h

BYTE

Cache Control register (see #01112)

53h

BYTE

Extended Cache Control register (see #01113)

54h

WORD

SDRAM Control Register (see #01114)

56h

BYTE

DRAM Extended Control register (see #01115)

57h

BYTE

DRAM Control register (see #01116)

58h

BYTE

DRAM Timing register (see #01117)

59h

7 BYTEs

Programmable Attribute Map registers 0-6 (see #01118)

60h

6 BYTEs

DRAM Row Boundary registers 0-5
each register N indicates cumulative amount of memory in rows 0-N (each 64 bits wide), in 4M units

66h

BYTE

reserved

67h

BYTE

DRAM Row Type High register (see #01213)

68h

BYTE

DRAM Row Type Low register (see #01119)

69h

7 BYTEs

reserved

70h

BYTE

Multi-Transaction Timer register
number of PCLKs guaranteed to the current agent before the 82439TX will grant the bus to another PCI agent on request

71h

BYTE

Extended System Management RAM Control register (see #01149)

72h

BYTE

System Management RAM Control register (see #01123)

73h

6 BYTEs

reserved

79h

BYTE

Miscellaneous Control register (see #01128)

7Ah

134 BYTEs

reserved

Note:

The Intel 82439TX chipset uses PCI configuration mechanism

See Also:

#00873