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Format of PCI Configuration data for Intel 82378 and 82379 ISA Bridges

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Offset Size Description

00h

64 BYTEs

header (see #00878)
(vendor ID 8086h, device ID 0484h)
(revision ID:
bit 7-4 : reserved
bit 3-0 : reserved
0011 = 82378ZB A0-step
1000 = 82379AB A0-step
)

40h

BYTE

PCI Control (see #01065)

41h

BYTE

PCI Arbiter Control (see #01066)

42h

BYTE

PCI Arbiter Priority Control (see #01067)

43h

BYTE

(82378ZB) PCI Arbiter Priority Control Extension Register
bit 0 : bank 3 fixed priority mode select (see also #01067)
0 = REQ2# has higher priority
1 = REQ3# has higher priority

44h

BYTE

MEMCS# Control (see #01068)

45h

BYTE

MEMCS# Bottom of Hole (address bits 23-16)

46h

BYTE

MEMCS# Top of Hole (address bits 23-16)

47h

BYTE

MEMCS# Top of Memory (address bits 28-21 == size in 2M increments, less 1)

48h

BYTE

ISA Address Decoder Control (see #01069)

49h

BYTE

ISA Address Decoder ROM Block Enable (see #01070)

4Ah

BYTE

ISA Address Decoder Bottom of Hole (address bits 23-16)

4Bh

BYTE

ISA Address Decoder Top of Hole (address bits 23-16)

4Ch

BYTE

ISA Controller Recovery Time (see #01087)

4Dh

BYTE

ISA Clock Divisor (see #01071)

4Eh

BYTE

Utility Bus Chip Select Enable A (see #01072)

4Fh

BYTE

Utility Bus Chip Select Enable B (see #01073)

50h

4 BYTEs

reserved

54h

BYTE

MEMCS# Attribute Register #1 (see #01074) attributes for 16K blocks from C0000h-CFFFFh

55h

BYTE

MEMCS# Attribute Register #2 (see #01074) attributes for 16K blocks from D0000h-DFFFFh

56h

BYTE

MEMCS# Attribute Register #3 (see #01074) attributes for 16K blocks from E0000h-EFFFFh

57h

BYTE

(82378) Scatter/Gather Relocation Base Adress (see #01075)
(82379AB) reserved

58h

8 BYTEs

reserved

60h

BYTE

(82378ZB) IRQ0# Route Control (see #01076)

61h

BYTE

(82378ZB) IRQ1# Route Control (see #01076)

62h

BYTE

(82378ZB) IRQ2# Route Control (see #01076)

63h

BYTE

(82378ZB) IRQ3# Route Control (see #01076)

64h

12 BYTEs

reserved

70h

BYTE

(82378) reserved
(82379AB, write-only) PIC/APIC Configuration Control (see #01077)

71h

BYTE

(82378) reserved
(82379AB, write-only) APIC Base Address Relocation (see #01078,MEM FEC00000h)

72h

14 BYTEs

reserved

80h

WORD

BIOS timer base address
bits 15-2 : bits 15-2 of BIOS timer port address
bit 1 : reserved (0)
bit 0 : timer enabled (if disabled, other bits ignored)

82h

30 BYTEs

unused???

A0h

BYTE

SMI Control (see #01079)

A1h

BYTE

reserved

A2h

WORD

SMI Enable (see #01080)

A4h

DWORD

System Event Enable (SEE) (see #01081)

A8h

BYTE

Fast-Off Timer (in minutes)

A9h

BYTE

reserved

AAh

WORD

active SMI Requests (see #01082)

ACh

BYTE

(82378ZB) Clock Throttle STPCLK# Low Timer
duration of STPCLK# low period in 32 microsecond units

ADh

BYTE

reserved

AEh

BYTE

(82378ZB) Clock Throttle STPCLK# High Timer
duration of STPCLK# high period in 32 microsecond units

AFh

81 BYTEs

reserved

See Also:

#01055,#01167