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Bitfields for Intel 82434LX/NX Error Command register

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Bit Description

7

assert SERR# on receiving target abort

6

assert SERR# on PCI data-write parity error

5

(NX only) assert SERR# on PCI data-read parity error

4

(NX only) assert SERR# on PCI address parity error

3

(NX only) assert PERR# on data parity error

2

enable L2 cache parity

1

enable SERR# on DRAM/L2 cache data parity error

0

assert PEN# on data reads; allow CPU to signal parity error via PCHK#

Note:

PCI command register bit 6 is master enable for bit 3.
PCI command bits 6 and 8 are the master enable for bits 7-4 and 1 bits 1-0 = 10 is not permitted.

See Also:

#01055,#01061