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Bitfields for Intel 82434LX/NX Secondary Cache Control

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Bit Description

7 - 6

secondary cache size
00 = none
01 = reserved
10 = 256K
11 = 512K

5

SRAM type
0 = standard SRAMs
1 = burst SRAMs

4

secondary cache allocation
0 = cache only CPU reads of memory with CACHE# asserted
1 = cache all CPU reads of cacheable memory

3

Cache Byte Control
0 = use single write enable and per-byte select lines
1 = use per-byte write enables on the cache

2

(NX only) SRAM connectivity
0 = disable CCS[1:0]# / CCS1# functionality
1 = enable CCS[1:0]# functionality to de-select async SRAMs, placing them in a low-power standby mode
1 = enable CCS1# functionality for burst SRAMs, indicating the lack of an external address latch

1

(LX only) Secondary Cache Write Policy
0 = write-through
1 = write-back (NX is always in write-back mode)

0

Secondary Cache Enable

See Also:

#01055,#01058