Bitfields for AMD-640 PCI Target Control register |
| Bit | Description |
|---|---|
|
7 |
slow memory decoding (must be set if fast back-to-back cycles enabled) |
|
6 |
add one wait state to TRDY# response on reads |
|
5 |
add one wait state to TRDY# response on writes |
|
4 |
reserved (0) |
|
3 |
assert STOP# after write timeout |
|
2 |
assert STOP# after read timeout |
|
1 |
enable sampling of PCI LOCK# pin |
|
0 |
force AMD-640 to initiate PCI arbitration if FRAM# not asserted within 16 PCI clocks of last GNT# |
|
See Also: |