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Bitfields for AMD-640 SDRAM Control Register

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Bit Description

7

 enable 4-bank interleave for 64-Mbit SDRAMs (when bit 5 set)

6

 enable SDRAM burst write

5

 enable SDRAM bank interleave (when set, reduces 3-line burst from 8-1-1-1-3-1-1-1-3-1-1-1 to 8-1...)

4

 reserved (0)

3

 SDRAM CAS# latency:
0 = latency 2
1 = latency 3

2 - 0

 SDRAM Operation Mode
000 = normal SDRAM
001 = enable NOP command
010 = convert CPU-to-DRAM cycles into All Banks Precharge command
011 = convert CPU-to-DRAM cycles into commands on MA[11:0]
100 = enable CAS#-before-RAS# cycles
101 = reserved
110 = reserved
111 = reserved

See Also:

#00983,#00999