Bitfields for OPTi 82C750 Vendetta (device 1) PCI master control |
| Bit | Description | ||||||
|---|---|---|---|---|---|---|---|
|
15 - 12 |
reserved | ||||||
|
11 |
interrupt request register recover enable | ||||||
|
10 |
DMA address and counter:
|
||||||
|
9 |
CPU/PCI master access ISA cycle retry enable | ||||||
|
8 |
CPU-to-PCI cycle AHOLD signal use enable (used only when bit 4 = 1) | ||||||
|
7 |
PCI master X-1-1-1 write enable | ||||||
|
6 |
PCI master X-1-1-1 read enable | ||||||
|
5 |
concurrent PCI master/IDE enable | ||||||
|
4 |
new AHOLD protocol enable | ||||||
|
3 |
PCI master non-contiguous byte enable | ||||||
|
2 |
reserved | ||||||
|
1 |
simultaneous hardware PMU and IDE function operation enable | ||||||
|
0 |
ISA refresh disable |
|
See Also: |