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Bitfields for OPTi 82C750 Vendetta (device 0) data path control

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Bit Description

41 - 47

reserved

40

DTY pin suspend enable

39 - 38

reserved

37

SDRAM refresh 0 sized bank RAS# disable

36

SDRAM control signal stepping enable

35

reserved

34 - 32

SDRAM mode
000 = normal
001 = NOP enable
010 = precharge all banks
011 = mode register enable
100 = CBR cycle enable
101 - 111 = reserved

31

SDRAM memory read access enable

30

CPU-to-PCI FIFO clear enable

29

PCI-to-DRAM FIFO clear enable

28

CPU-to-DRAM FIFO clear enable

27

82C750 register write disable

26 - 15

reserved

14

PCI master/ECC generate NMI disable

13 - 12

reserved (1)

11

memory parity checking enable

10

reserved

9

CPU DRAM write byte merge enable

8

MD bus pull-up resistor disable

7

PCI CPU write 6DW FIFO enable

6

DRAM PCI read 24DW FIFO enable

5

DRAM PCI write 24DW FIFO enable

4

DRAM CPU write 8QW FIFO enable

3

82C750 memory read access:
0 = SDRAMreserved
1 =

2 - 1

reserved

0

82C750 memory read access:
0 = FP mode
1 = EDO/SDRAM

See Also:

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