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Bitfields for OpenHCI "HcInterruptEnable" and "HcInterruptDisable" registers

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Bit Description

31

MIE master interrupt enable

30

OC ownership change

29 - 7

reserved

6

RHSC Root Hub status change

5

FNO frame number overflow

4

UE unrecoverable error

3

RD Resume Detect

2

SF start of frame

1

WDH HcDoneHead writeback

0

SO scheduling overrun

Note:

Writing a 1 bit to HcInterruptEnable enables the corresponding interrupt, while writing a 1 bit to HcInterruptDisable disables it; zero bits are ignored. On reading, both registers return the same value, which reflects the currently enabled interrupts.

See Also:

#00902