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Bitfields for PCI Configuration Bridge Control Register

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Bit Description

7

enable fast back-to-back cycles on secondary bus

6

reset secondary bus

5

master abort mode on secondary bus

4

reserved

3

VGA enable (when set, forward VGA memory and I/O ranges to seconary bus)

2

ISA enable

1

reserved

0

enable parity error response

See Also:

#00878,#01131