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Bitfields for PCI Power Management Capabilities

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Bit Description

15

reserved (0)

14 - 12

PME# support
bit 12 : PME# can be asserted from power state D0
bit 13 : PME# can be asserted from power state D1
bit 14 : PME# can be asserted from power state D2

11

reserved (0)

10

D2 power state supported

9

D1 power state supported

8

full-speed clock is required in state D0 for proper operation
(if clear, device may be run at reduced clock except when actually being accessed)

7 - 6

dynamic clock control support
00 : not bridge, no dynamic clock control, or secondary bus' clock is is tied to primary bus' clock
01 : bridge is capable of dynamic clock control
10 : reserved
11 : secondary bus has independent clock, but dynamic clock not supported

5

device-specific initialization is required

4

auxiliary power required for PME# generation

3

PCI clock required for PME# generation

2-0

specification version
001 = v1.0; four bytes of power management registers

Note:

This information is from the v0.93 draft of the specification and is subject to change.

See Also:

#00884,#00886,#00887