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Format of PCI Configuration Status Register

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Bit Description

3 - 0

reserved (0)

4

new capabilities list is present (first entry pointed at by byte at 34h or 14h)

5

capable of running at 66 MHz

6

UDF supported

7

capable of fast back-to-back transactions

8

data parity error reported

10 - 9

device select timing
00 - fast
01 - medium
10 - slow
11 - reserved

11

signaled target abort

12

received target abort

13

received master abort

14

signaled system error (device is asserting SERR# line)

15

detected parity error (set even if parity error reporting is disabled)

Note:

Bits 12, 13 and 15 are cleared by writing a 1 into the corresponding bit.

See Also:

#00878,#00879