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Code Mnemonic Description
0F BE / r MOVSX r16, r/m8 Move byte to word with sign-extension
0F BE / r MOVSX r32, r/m8 Move byte to doubleword, sign-extension
0F BF / r MOVSX r32, r/m16 Move word to doubleword, sign-extension

Description
Copies the contents of the source operand (register or memory location) to the destination operand (register) and sign extends the value to 16 or 32 bits (see Figure 6-5 in the Intel Architecture Software Developer's Manual, Volume 1). The size of the converted value depends on the operand-size attribute.
Operands Bytes Clocks
reg, reg 3 3 NP
reg, mem 3 + d(0, 1, 2, 4) 3 NP
(Note: destination reg is 16 or 32-bits; source is 8 or 16 bits)

Flags
ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF unaffected
VM unaffected ZF unaffected
RF unaffected AF unaffected
NT unaffected PF unaffected
IOPL unaffected CF unaffected
OF unaffected