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MOV - Move to/from Debug Registers

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Code Mnemonic Description
0F 21/ r MOV r32, DR0 Move debug register to r32
0F 21/ r MOV r32, DR1 Move debug register to r32
0F 21/ r MOV r32, DR2 Move debug register to r32
0F 21/ r MOV r32, DR3 Move debug register to r32
0F 21/ r MOV r32, DR4 Move debug register to r32
0F 21/ r MOV r32, DR5 Move debug register to r32
0F 21/ r MOV r32, DR6 Move debug register to r32
0F 21/ r MOV r32, DR7 Move debug register to r32
0F 23 / r MOV DR0, r32 Move r32 to debug register
0F 23 / r MOV DR1, r32 Move r32 to debug register
0F 23 / r MOV DR2, r32 Move r32 to debug register
0F 23 / r MOV DR3, r32 Move r32 to debug register
0F 23 / r MOV DR4, r32 Move r32 to debug register
0F 23 / r MOV DR5, r32 Move r32 to debug register
0F 23 / r MOV DR6, r32 Move r32 to debug register
0F 23 / r MOV DR7, r32 Move r32 to debug register

Description

Moves the contents of a debug register (DR0, DR1, DR2, DR3, DR4, DR5, DR6, or DR7) to a general-purpose register or vice versa. The operand size for these instructions is always 32 bits, regardless of the operand-size attribute. (See Chapter 14, Debugging and Performance Monitoring, of the Intel Architecture Software Developer's Manual, Volume 3, for a detailed description of the flags and fields in the debug registers.)

The instructions must be executed at privilege level 0 or in real-address mode.

When the debug extension (DE) flag in register CR4 is clear, these instructions operate on debug registers in a manner that is compatible with Intel386 and Intel486 processors. In this mode, references to DR4 and DR5 refer to DR6 and DR7, respectively. When the DE set in CR4 is set, attempts to reference DR4 and DR5 result in an undefined opcode (#UD) exception. (The CR4 register was added to the Intel Architecture beginning with the Pentium processor.)

At the opcode level, the reg field within the ModR/M byte specifies which of the debug registers is loaded or read. The two bits in the mod field are always 11. The r/m field specifies the general-purpose register loaded or read.
Operands Bytes Clocks
r32, cr32 3 4 NP
cr32, r32 3 12/22 (cycles depend on which special register) NP
r32, dr32 3 2/12 (cycles depend on which special register) NP
dr32, r32 3 11/12 (cycles depend on which special register) NP
r32, tr32 3 - NP
tr32, r32 3 - NP

Flags

ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF undefined
VM unaffected ZF undefined
RF unaffected AF undefined
NT unaffected PF undefined
IOPL unaffected CF undefined
OF undefined