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Code Mnemonic Description
E4 ib IN AL, imm8 Input byte from imm8 I/O port address into AL
E5 ib IN AX, imm8 Input byte from imm8 I/O port address into AX
E5 ib IN EAX, imm8 Input byte from imm8 I/O port address into EAX
EC IN AL, DX Input byte from I/O port in DX into AL
ED IN AX, DX Input word from I/O port in DX into AX
ED IN EAX, DX Input doubleword from I/O port in DX into EAX

Description
Copies the value from the I/O port specified with the second operand (source operand) to the destination operand (first operand). The source operand can be a byte-immediate or the DX register; the destination operand can be register AL, AX, or EAX, depending on the size of the port being accessed (8, 16, or 32 bits, respectively). Using the DX register as a source operand allows I/O port addresses from 0 to 65,535 to be accessed; using a byte immediate allows I/O port addresses 0 to 255 to be accessed.

When accessing an 8-bit I/O port, the opcode determines the port size; when accessing a 16- and 32-bit I/O port, the operand-size attribute determines the port size.

At the machine code level, I/O instructions are shorter when accessing 8-bit I/O ports. Here, the upper eight bits of the port address will be 0.

This instruction is only useful for accessing I/O ports located in the processor's I/O address space. See Chapter 9, Input/Output, in the Intel Architecture Software Developer's Manual, Vo l u me 1 , for more information on accessing I/O ports in the I/O address space.
Operands Bytes Clocks
al, imm8 2 7 NP
ax, imm8 2 7 NP
eax, imm8 2 7 NP
al, dx 1 7 NP
ax, dx 1 7 NP
eax, dx 1 7 NP

Protected mode:
Operands Bytes Clocks
acc, imm 2 4/21/19 NP
acc, dx 1 4/21/19 NP

cycles for: CPL <= IOPL / CPL > IOPL / V86

Flags
ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF unaffected
VM unaffected ZF unaffected
RF unaffected AF unaffected
NT unaffected PF unaffected
IOPL unaffected CF unaffected
OF unaffected