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IMUL - Signed Multiply

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Code Mnemonic Description
F6 /5 IMUL r/m8 AX AL * r/m byte
F7 /5 IMUL r/m16 DX:AX AX * r/m word
F7 /5 IMUL r/m32 EDX:EAX EAX * r/m doubleword
0F AF / r IMUL r16, r/m16 word register word register * r/m word
0F AF / r IMUL r32, r/m32 doubleword register doubleword register * r/m doubleword
6B / r ib IMUL r16, r/m16, imm8 word register r/m16 * sign-extended immediate byte
6B / r ib IMUL r32, r/m32, imm8 doubleword register r/m32 * sign-extended immediate byte
6B / r ib IMUL r16, imm8 word register word register * sign-extended immediate byte
6B / r ib IMUL r32, imm8 doubleword register doubleword register * sign-extended immediate byte
69 / r iw IMUL r16, r/m16, imm16 word register r/m16 * immediate word
69 / r id IMUL r32,r /m32, imm32 doubleword register r/m32 * immediate doubleword
69 / r iw IMUL r16, imm16 word register r/m16 * immediate word
69 / r id IMUL r32, imm32 doubleword register r/m32 * immediate doubleword

Description
Performs a signed multiplication of two operands. This instruction has three forms, depending on the number of operands.

One-operand form. This form is identical to that used by the MUL instruction. Here, the source operand (in a general-purpose register or memory location) is multiplied by the value in the AL, AX, or EAX register (depending on the operand size) and the product is stored in the AX, DX:AX, or EDX:EAX registers, respectively.

Two-operand form. With this form the destination operand (the first operand) is multiplied by the source operand (second operand). The destination operand is a general-purpose register and the source operand is an immediate value, a general-purpose register, or a memory location. The product is then stored in the destination operand location.

Three-operand form. This form requires a destination operand (the first operand) and two source operands (the second and the third operands). Here, the first source operand (which can be a general-purpose register or a memory location) is multiplied by the second source operand (an immediate value). The product is then stored in the destination operand (a general-purpose register).

When an immediate value is used as an operand, it is sign-extended to the length of the destination operand format.

The CF and OF flags are set when significant bits are carried into the upper half of the result. The CF and OF flags are cleared when the result fits exactly in the lower half of the result.

The three forms of the IMUL instruction are similar in that the length of the product is calculated to twice the length of the operands. With the one-operand form, the product is stored exactly in the destination. With the two- and three- operand forms, however, result is truncated to the length of the destination before it is stored in the destination register. Because of this truncation, the CF or OF flag should be tested to ensure that no significant bits are lost.

The two- and three-operand forms may also be used with unsigned operands because the lower half of the product is the same regardless if the operands are signed or unsigned. The CF and OF flags, however, cannot be used to determine if the upper half of the result is non-zero.
Accumulator Operands Multiplies Bytes Clocks
r8 2 11 NP
r16 2 11 NP
r32 2 10 NP
mem8 2 + d(0 - 2) 11 NP
mem16 2 + d(0 - 2) 11 NP
mem32 2 + d(0 - 2) 10 NP

implied multiplicand operand (multiplier) result
AL * byte = AX
AX * word = DX:AX
EAX * dword = EDX:EAX

2 and 3 operand Multiplies

Operands Bytes Clocks
r16, imm 2 + i(1, 2) 10 NP
r32, imm 2 + i(1, 2) 10 NP
r16, r16, imm 2 + i(1, 2) 10 NP
r32, r32, imm 2 + i(1, 2) 10 NP
r16, m16, imm 2 + d(0 - 2) + i(1, 2) 10 NP
r32, m32, imm 2 + d(0 - 2) + i(1, 2) 10 NP
r16, r16 2 + i(1, 2) 10 NP
r32, r32 2 + i(1, 2) 10 NP
r16, m16 2 + d(0 - 2) + i(1, 2) 10 NP
r32, m32 2 + d(0 - 2) + i(1, 2) 10 NP


Flags

ID unaffected DF unaffected
VIP unaffected IF unaffected
VIF unaffected TF unaffected
AC unaffected SF undefined
VM unaffected ZF undefined
RF unaffected AF undefined
NT unaffected PF undefined
IOPL unaffected CF For the one operand form of the instruction, sets when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, sets when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size
OF For the one operand form of the instruction, sets when significant bits are carried into the upper half of the result and cleared when the result fits exactly in the lower half of the result. For the two- and three-operand forms of the instruction, sets when the result must be truncated to fit in the destination operand size and cleared when the result fits exactly in the destination operand size